Good morning,

This week’s Stratechery Interview is with Synopsys CEO Sassine Ghazi. Synopsys is a leader in the electronic design automation (EDA) space, i.e. they make the software that companies use to design chips. Synopsys was founded in 1986 by Aart de Geus, David Gregory, and Bill Krieger, just a few months before TSMC, and have been an essential part of the fabless value chain; de Geus was CEO of the company until January of this year, when he transitioned to executive chairman and was succeeded by Ghazi.

In this interview, which was conducted in person in Taipei earlier this week, we discuss Ghazi’s career and the overall arc of Synopsys, and how chip design has changed from drafting boards to software to AI. We also touch on the rise of IP blocks as a business model, how Synopsys and TSMC have had to become more integrated over time, the role of verification in helping designers let go of transistor-level control, and why Synopsys is moving into system design and acquired Ansys. I did not, by request, ask about regulatory issues around China and the Ansys acquisition, or Intel.

As I noted, this interview was in person, so there was a lot more back-and-forth than usual. To that end, all Stratechery content, including interviews, is available as a podcast; click the link at the top of this email to add Stratechery to your podcast player.

On to the Interview:

An Interview with Synopsys CEO Sassine Ghazi About Designing Chips

This interview is lightly edited for clarity.

Background

Sassine Ghazi, welcome to Stratechery.

SG: Thank you.

I’m very excited to talk to you because, while I’m broadly familiar with Electronic Design Automation (EDA) software, it’s hard not to in this space — well, maybe I’m overstating it because maybe not a lot of people talk about this, I haven’t covered it directly or covered you guys directly. So my goal here is to be a bit of a stand-in for my audience and hopefully we can learn a lot about not just the industry and Synopsys but also you, if that sounds good to you.

SG: That sounds great.

Great. So I do have a meta question and maybe it gets to this, why are you doing these podcasts? You did Acquired over the summer, it was a great episode, we’ll put a link to it, with Aart [de Geus], your predecessor as CEO and founder of the company. What’s the big picture? What’s your view of the world that’s like, “You know what, we should go talk to Ben, we should do these sorts of things”?

SG: When I look at Synopsys, we’re about a 40-year-old company, and I want to say for a big chunk of those four decades we’ve been very much under the radar when it comes to the impact and the value that we are in that supply chain of semiconductors. In the recent years, in the last five to ten years, given some of this slowdown with Moore’s Law, the industry has been looking for anywhere you can achieve the performance, the energy efficiency for the next generation product, and EDA stepped up. We filled that gap of what is possible through process technology, what is possible through our customer architecture and design, and EDA as an industry as a whole came in very strongly in adding that value.

Now, that’s one aspect of what drove the growth for our company and our industry in general. The second part is engineering is being redefined. When you look at the modern chip, it’s no longer the same chip approach workflow methodology that was designed say five years ago, it’s a system that you’re designing, and Synopsys is going through that transformation of providing solutions not only at the silicon level but a silicon-to-system level solution.

I think that was a good overview, we’re going to get into all those pieces. But before that, I do always like to start with you. So you said Synopsys started 40 years ago, you’re a young-looking guy and I think it’s very clear you weren’t there at the beginning. Where did you get started? How did you end up at Synopsys? What was your life path?

SG: So I’ve been at Synopsys for 26 years.

Yeah, see, that makes more sense.

SG: (laughs) My career has gone through, I want to say, four phases of functions. The first phase was about six years of engineering work post-grad school.

Did you do electrical engineering in college then?

SG: I did electrical undergrad, electrical grad school.

What made you want to do electrical engineering? Was it that you were just great at computers as a kid? What’s the story there?

SG: It was much simpler, my dad was an electrical engineer.

Oh, there you go.

SG: “That’s a great field, why don’t you go study and do it?”, and actually it is part of the journey, because when I did my electrical engineering undergrad, I did very good in terms of getting good grades and graduated with honor, etc., but I wasn’t sure if I liked it or not.

Right. Many such stories where kids follow their dad’s path.

SG: Yeah, that’s right, and when you see people really in love with what they’re studying, I was not feeling it. So I did my Master’s in control and systems still in the electrical engineering.

But up a level.

SG: Right, up a level, and I liked it. But then I saw a change happening in the market, which is all driven by more very large scale digital design to be able to design much bigger chips. So I started my PhD in computer engineering, so I pivoted a little bit.

And the computer engineering with the idea of these EDA systems, that was already on the mind?

SG: Exactly, exactly, exactly. Then I did an internship and I fell really in love with the industry, then I dropped out.

Good choice, I think it worked out pretty well.

SG: Two years into it, and I started at Intel. Then I was at Synopsys for a total of about six years as engineering work, then my career from that point, I was just flexible when I was asked to move. So I was asked to move from engineering work to manage one of our top customers, and so I pivoted to sales. Did not want to do it, but I’m like, “Hey, it’s still early in my career, what the heck? I’ll give it a try”.

The single best pivot if you want to end up in your current position, in many respects.

SG: Right. Then I was there for about 14 years, then my next ask was to move to product development as a general manager.

Quick question, who were you selling to in this era? So this must have been what, the 2000s?

SG: In the 2000s, yes. Actually, it’s amazing how much the world changed.

Right, that’s why I’m curious. What was your market at that point versus now?

SG: Our number one customer at the time when I moved to sales was Motorola. And now when you look at Motorola—

Not your number one customer anymore?

SG: (laughing) No.

(laughing) That’s all I asked, I just asked where their ranking was, nothing else.

SG: Right, because the world changed a lot because they were a system company designing their own chips and, at the time, Synopsys was just at the chip level. So we sell EDA, we just started in the IP business.

EDA

Well, let’s do this, let’s back up. When you joined Synopsys in 1998, they started in 1986, I think. It was in the ’80s.

SG: The 80s.

Yeah, the 80s. So what was Synopsys’ product at the beginning and what have been the big transitions? Because you’re about to talk to one, but that’s transition three, what were the early ones?

SG: So Art, our founder, in the early ’80s, the chip design process was very manual.

Drafting tables and drawing out actual logic gates.

SG: And it was good enough, it was okay because the largest chip was in the order of thousands of devices or transistors, so it was manageable with some CAD tools that you can visualize and draw lines to connect the transistor to another transistor, etc. Then the idea of Synopsys at the time, “Can you describe the chip intent in a language, that software language, and have it synthesize it into what a human would draw manually”?

Is it fair to say that when you use the word “synthesize”, that’s just like the chip version of compile?

SG: Exactly, exactly.

And so you are building the compiler for chips?

SG: So you’re building a compiler in a hardware description language.

Right.

SG: So you’re describing the intent of the hardware in a specific language. It can be RTL, Verilog, etc. So when you write things in code, you’re far more efficient than can you compile it, synthesize it. That’s what’s called Design Compiler, that was our first product, DC, Design Compiler. “Can you compile it into an output that can be manufactured so it does not violate manufacturing rules, etc.?”

Right, and so you’re putting in all the constraints around the manufacturing process and it’s fitting it in that box?

SG: Exactly. You’re putting manufacturing input and you’re putting design input and the targets in terms of power, performance, etc.

So were all these heuristics that did this, were those all hand-coded back then because you put in all the things? How did you balance those trade-offs computationally?

SG: It started as hand-coded, then you start building libraries. It’s like, “Okay, there’s no reason to keep re-coding for certain functions”. Then you start building libraries and Design Compiler was the compiler, then we created at the time, if I’m not mistaken, that was the name at the time.

Don’t worry, we’ll let you off the hook. You weren’t there, but I do appreciate the history all the same.

SG: It was DesignWare Library that goes with Design Compiler. Then at the time the customer’s resistance was, “Will Design Compiler give me a performance or power or area as good as a human hand-crafted design?”.

Right, a very cute concern in retrospect.

SG: Correct, exactly. Imagine if it’s still, right now we’re talking about 200, 300 billion transistors, there’s no way you can do it without, of course, the technology. So that was the start of Synopsys. The second focus was, “Can you verify these chips?”.

Right, because that’s how you solve that problem.

SG: Exactly.

You don’t actually let a human go through and trace every transistor, they could never do it.

SG: Exactly, so you design it. Now, can you verify it? Then the third was happening right around when I joined Synopsys, the process technology got more complex, you’re putting more devices and more transistors.

And just for context, 1998, the leading chip was the Intel Pentium II, which was 35 microns or something like that.

SG: Yeah, that’s what it was.

Yeah, I was obsessed with the Celeron 300 or 300A, because you could overclock it to 450.

SG: Yeah, that’s right, exactly. Then Synopsys at the time felt, “Okay, you can compile a design, you can verify it, but can you implement it once you go into the actual translating into the physical layers of implementation?”.

Right. So it’s basically a shift from design constraints to physical constraints got introduced?

SG: Exactly. So those were the three steps of evolution that Synopsys took in the first two decades.

Is this when you started getting into things like Emulation and things along those lines? Or was that a later step?

SG: The concept was there but it was not really adopted because—

Hardware wasn’t good enough or what?

SG: Yeah. And you could get through certain verification techniques, still enough coverage and speed to verify what you’re designing, and what’s actually really remarkable in our industry, innovation is triggered by complexity. Whenever you hit the wall, “Okay, it’s taking too long, the chip is not working or I’m unable to jump to the next innovation step or process”, or whatever, then you look for other techniques.

That gets back to your high level pitch, which is, for decades, the industry has depended on Moore’s Law, and your bid is, “We can continue the acceleration, but we’re going to look in other areas like the software and design”.

IP

SG: Exactly, so then the next step of transformation the company and the industry went through was IP.

Good, now we’ve come full circle, we’ve gotten back to where we were.

SG: Because our IP business is about 25, 26 years investment that started in the company and the concept there was for, if you look at your PC, and at the time it was just early days of the mobile, there are some industry standards that started to surface, a USB, a how to connect the chip to the outside world, chip-to-chip.

All the I/O stuff.

SG: All the I/O stuff. So the concept was they’re the same standard so the customers are putting their skills to read this or design this.

Yeah, total waste of time.

SG: Exactly the same thing, what a waste, can we be the one providing it for them?

And then now suddenly you have royalties on all the chips that go forward?

SG: Actually Synopsys’s type of IP, what is called the Interface IP, the market does not have royalty in it. So, it’s different than the processor IP.

Got it.

SG: Or what’s called Foundation IP, because those pieces, they have royalty. So for us it’s a use fee. Not only us, for the industry of Interface IP, it’s a use fee. So anytime the customer’s designing a new chip, they come and they license the IP.

Got it, okay. And then that applies for the whole chip lifetime?

SG: Yes. Why? Because the way they view it is Synopsys, I can design that same IP.

Right, and that’s a potential hurdle for people using your software. It’s like, “This is actually going to cost me a lot in the long run”.

SG: Right, so we started with lowering the barrier at the customer. Really the selling pitch at the time, “We can do it faster and cheaper than you can, the customer, because we’re designing it once and we’re selling it many, many times”, so it provided them that flexibility on their resources were to put their resources.

Yeah. You got all the leverage, but you didn’t have to overplay it.

SG: At the time, and actually even for the first 10, 15 years, our biggest competitor in IP was the customer. Because if they-

Have their own USB libraries.

SG: Yeah, they have the team already, and they come and say, “I already have my team”. Where the inflection point happened in IP, when the customer started looking for process technology optionality, meaning, “I’m doing chip A on foundry A, but I want to move that chip to foundry B.”

So you’re one level up on abstraction because you’ve already implemented it for both processes.

SG: Yeah, with IP. If you buy the USB from Synopsys and you want to use it on a TSMC, and tomorrow you want to go to—

UMC or whatever, yeah.

SG: —to Intel, we have that portfolio on every process and foundry. So it’s really optionality for customer, and optimality, because you can optimize your skills, your resources to put them in.

How much of a lift is it for you then when one of your customer or one of your foundry partners goes to a new process? Is there just a massive team that has to go through and all this IP has to be updated?

SG: It is.

That’s sort of what you’re getting paid for is maintaining those libraries.

SG: That is right now, the biggest challenge in IP. One, is the ability to port these complex libraries to the latest process technology, because process technology is not getting easier. So going from a 4nm to 3nm to 2nm is just more complex, so that’s challenge one. Challenge two, with heterogeneous integration, Multi-Die, there’s a new set of standards that fewer customers are needing them as soon as possible, before the standard is becoming a standard. So they’re thinking it at version 0.1, and they expect to put it on their chip and go to market.

So you had this sort of backwards compatibility challenge where even once it gets to the standard, use still might have a few trailing bits for the old-

SG: So before, a standard used to last about four to six years, and you release a standard to the customer or you go on a test chip with foundry around 0.7 to 0.9 version of the standard. Right now you’re at the 0.1, having a test chip expectation, and then those standards instead of four to six years, they’re shrinking to about two to three years. Because bandwidth, bandwidth, especially for AI, data center type of IP, so it’s a different pace and different complexity.

How do you think about the balance of your IP business versus your traditional software business? I mean, you had high growth in IP. Is that sort of the higher — in the long run, that’s going to be more and more important? I’m not saying it’s not important now, it’s a big part of your business, but smaller than the software side.

SG: Rough numbers, rough numbers, about 75% of our business is the traditional Design Automation, and 25% is IP.

Right, but IP is growing faster.

SG: So IP, what we expect in terms of growth, is mid-teens. Design Automation, double digits. So you can say double digits is 10 to 12%, the other one’s 15 to 17%, depending on where you are. We’ve been performing at that level, but the Design Automation has two components. It has the traditional software that we talked about, and then there’s another piece which is the hardware emulation, and that’s growing in its importance significantly, giving the complexity.

TSMC

Yeah. Okay, we’ll come back to that, because I think that we will circle back to that, but I have just sort of a little, one more historical question. You started within months of TSMC, and is maybe to go back to the meta question of, “Why this podcast?”, everyone knows the importance of TSMC. People have woken up to the importance of say like an ASML, maybe a little less so as far as a LAM or an Applied Materials. Is there a bit of waving our flags saying, like, “Hey, we were along for this ride too, and this whole fabless revolution, you need software to do that, and that’s sort of what we’ve provided”.

SG: It depends who you’re talking to. If you talk to semiconductor companies at the engineering level all the way to CEO, they know we are critical. They know it, there’s no debate. Believe it or not, we are so intimate with our customers that before they finalize a roadmap item, we’re working with them to see what is possible. “Can you achieve what you want to achieve with your architecture, with the process technology that you selected?”, or you can deliver to a product, but with a different options in terms of technology, architecture, etc. We are at that very, very early stage with customers.

So the customers, they completely get how mission-critical we are to their success, the market is starting to get it. Today, when you look at Synopsys, it depends on the day, anywhere between a $75 to a $90-ish billion dollar market value, we’re being recognized how critical we are and resilient our business model is.

Is there a bit where that window when you started was just the perfect window? Because you’ve traditionally been digital-only, and then you’re sort of like as this fabless model is coming up, and the old IDM model, everything’s integrated, they all have their own software, they have their own manufacturing, the design, and there’s a lot of advantages that came from that for a long time, obviously lots of challenges the more complex things get, but you are there in this modular world. Again, really sort of a sister company to TSMC all along.

SG: Actually, there are some fun stories. If you listen to Aart describing the early days with [TSMC Founder] Morris Chang.

Actually, I thought about framing that question as, “If Aart and Morris Chang are sitting around over beers, who owes who what?”

SG: It’s funny, actually, believe it or not, they do laugh and joke and have that conversation, that Synopsys started with simplifying and providing a higher level abstraction of a chip, which enabled customers to design a very large scale chips with redefining how chip is designed, that was Synopsys. TSMC lowered the bar on customers not having to make that huge capital investment and outsource the manufacturing.

It’s two peas in a pod.

SG: Exactly, exactly what you said. It started around the same time. The IDM transformation, most IDMs for the first 20 years of Synopsys existence, they had their own EDA tools.

Yep. Some of them even longer.

SG: Yeah, exactly. The reason they had it, they had their process technology, and they know how essential is the EDA need to co-optimize with process technology, so they had both, and of course they had their architecture design, etc. As companies started outsourcing their manufacturing, it made no sense for them to keep their EDA, they completely outsourced EDA.

Now I’ll say the last 10-ish years or so, especially when you move from a 5nm and below, things have changed. The relationship was Synopsys-semiconductor company and Synopsys-say manufacturing, say TSMC. But it was never at the time, Synopsys-semiconductor company-TSMC. It was just we work with the semi, then you work with foundry, we enable.

Yeah. It’s sort of like a step-by-step process, you start here, then you go there.

SG: Right, because it was good enough.

And TSMC’s like there’s these new features like, “Okay, we’ll put them in the software, all good, lets do XYZ”.

SG: Exactly. So we work very hard with TSMC to enable the new features, we certify them with TSMC, then the customer goes to TSMC, gets process technology, they come to Synopsys, they get the tool to run it. Up until about 5-ish nanometer, where the entitlement is called that you’re getting out of the process technology was not sufficient anymore for the cost of going to that next node.

You had to basically integrate to a certain extent.

SG: Right, they want to squeeze more mileage, and then it started bringing a trio of optimization. Today, I cannot think of a customer who’s designing at a 3nm and below, that we don’t have a three-way, tight collaboration with the customer and TSMC to set targets on process technology, on architecture, on EDA and IP, in order to achieve the power, the performance, the area.

Do you see this being just like a line in time? Will there be a point where — a lot of people argue that trailing edge stuff is just going to stop at 28nm, maybe it’ll go down to 14nm or whatever, but once you cross the FinFET line, costs go up a lot. But you’re speaking to another point, which is because the complexity goes up so much, it’s an IDM model with all independent companies to a certain extent, and it’s all sort of intermingled. Those 5nm/7nm, will they ever be modularized and re-broke into pieces? Or is that line going to be a permanent one?

SG: Yeah, there will be modularization. If you look today at the modern, say an AI accelerator — or actually zoom out, look at a phone or a PC or a car, etc., you are going to need to have the compute part of your electronic system at the most advanced process technology you can get. Expensive, not too many companies can afford it. Sometimes you question the benefit of the yield, the reliability, but—

You’ve got to be there.

SG: That’s where the industry has been, you’ll figure it out.

Yeah, but the question I’m wondering is, that’s for sure, so if you’re on 3nm today, you’re on the cutting edge, or you’re looking at 2nm, or a 16A or whatever it might be. But when you say you have these 7nm fabs, and I think one of TSMC’s challenges, they’re not maybe as utilized as they would like, will we get to a point where medium-edge customers will call them?

SG: Yeah, yeah.

It’s much easier to just walk up and use it, they don’t have to be deeply involved in that design, you will have simplified things to the extent that they can just—

SG: For sure. Where we put significant amount of our R&D is-

Productizing these super complex integrated things.

SG: But before you get there, the latest process, minus one, minus two, is where most of our R&D goes. Why? Because they’re still evolving. Even if you look at the 3nm, 4nm, 5nm, it’s not like it stopped the optimization possibility between process and the EDA. That’s why you have PDK 1.1, they don’t stop at 1.0, and say, “This is it, we’re not doing anymore.” It’s a continuous improvement, but then it runs out of its benefit. If you go down to, let’s say, 7nm, our cost of supporting a customer from a product development goes down drastically, because it’s been flushed out.

It’s like the software version of the foundry model, basically.

SG: It is the software version of the foundry model.

AI Design

I halted your progress, I think, in the 2000s, somewhere around then. We talked about the EDA software being human designed. Computers were doing it, but it was heuristics like that. When was the big shift to machine learning, and where the computer is really just taking on a huge burden in terms of how this chip design happens?

SG: From the early days of Synopsys throughout our existence, what we do really is, we have algorithms that they optimize functions of the chip, it’s a continuous R&D investment and improvement. Around the 2017 timeframe, a R&D team at Synopsys came to me because I was responsible for the product development.

Got it, you definitely moved on from sales at that point if that’s the case.

SG: Yeah, that’s right. In 2016, Google wrote a paper about deep reinforcement learning and how it has the ability to optimize a very large space of variables. That team came to me and was like, “It’s very simple”.

Yeah, we have a lot of variables.

SG: “We have a huge space of variables, can we use a similar—”

And that’s around FinFET time, so now you have 3D and the complexity is massively increasing.

SG: Complexity was massive. And they’re like, “Can we see if that concept can apply to…”, chip design has many phases, and the most complex phase is what’s called the implementation of the chip, because this is where you’re optimizing various foundry input, library input, design input into millions.

Is this towards the end of the process or where in that?

SG: It’s in the middle of the process. You already synthesize and compiled, now you’re putting all the foundry rules into it to see is it possible to implement it, that’s the chunk that takes the most time.

And takes the most time in terms of human work or in supercomputers running these?

SG: Actually, it’s a really fascinating space, because what can the EDA tool handle will dictate what our customer can do from an architecture point of view. To give you an example, an EDA product, let’s say, it has a sweet spot at the time of handling, let’s say, 1 million gates. The reason they say 1 million at the time is, it takes about a week to run, so if you’re an engineer, you define the parameters.

It’s a variable that has nothing to do with the actual chip or physics, but time.

SG: So, then the customer limits the way they partition their chip to 1 million gates. Is it the optimal architecture? No. But they say, “That’s the maximum I have with my tools, if you put two million, it may take a month to get results”. Let’s say the results are bad, you run multiple jobs at the same time.

It’s a batching problem, in some respect, yeah.

SG: It’s a batching problem and an ongoing engineering creativity to say, “What can I do?”. With AI, what was amazing is, you look at this massive space of optimization and you allow the machine to look at that space and does its heuristics and say, for the following outcome you’re giving me to target, this is the best recipe in order to get you there. So, we were able to drastically reduce the engineering time to figure out a recipe and let AI do it.

Just because it was exploring the latent space.

SG: It’s exploring the space. Now believe it or not, at the time, when we introduced the product, we had a prototype working within months. I remember that small group, I had to isolate them even inside the company, because otherwise they’d get squashed. “No, no, there’s nothing there”, but within a few months, six-ish to nine months, they had a prototype, that they were running it on every customer design that we had in-house, and for every design it was providing much better results. You cannot go to market with a prototype, so we were like, “Okay, how do we package it in a way that’s usable by our customers?”, we went into selecting about five, six customers at the time, around 2019 timeframe, and then we went to market in 2020. The biggest resistance at the time is, “I don’t know what the machine is doing”.

Yeah, we don’t either!

SG: No, really, that was the answer! At the time, I remember the customers are like, “But I want the input or the output that this machine is producing, because you cannot understand it. It’s just some crazy variables that it set.

This really then raised up the importance of the validation.

SG: What it raised was that there is the next level of optimization to deal with the complexity by using, in this case, a reinforcement learning, two things happened. Instead of the customer limited to design, let’s say the 1 million gate, they’re able to design bigger, so they started thinking differently of their architecture. It’s like, “Oh, now I can do more”, so they have more flexibility. To the importance of what’s called sign-off, once you’re done with that step of the flow, you need to trust that the results are actually going to work — your performance, your power, your manufacturability. It brought in that importance once you’re done with AI, that whatever outcome, it’s signed off as good as the previous flow without AI. Given the complexity increased, and the more transistors you can design, and larger the chip, it brought in the need and the higher importance of validation through hardware-accelerated verification, emulation, prototyping, etc.

You mentioned that month timeline. Is that month still there, or you’re just more sure that it’s right, or did that month also get shrunk down? Or is that the validation phase, is that have 2 million transistors, it could take a month to do? Did that shift that to the backend? You were able to do much more virtually?

SG: No. Instead of having serial process, you are able to do things upfront, let me explain.

A traditional workflow before AI, let’s say an engineer is setting up various variables to get to a certain performance target, it’s serial work. Even though they invoke five, six experimentations, they wait a week to see the results, then they tune the recipe, then they wait another week to do the results. With AI, you needed two things. You needed more machine so you can do a much broader space of exploration, and you need more EDA software to run. Instead of, let’s say, four or five jobs per engineer, you may run thousands.

It’s just massively parallelizing the process for you.

SG: Exactly.

It used to be a very serial process.

SG: So, instead of being serial and discovering what’s possible, it became much broader, but it required a lot of compute and a different methodology to do the work.

It’s a good stand-in for just how AI works in general.

SG: Exactly. But at the time, around 2018, 2019, 2020, what the customer were struggling with, “But that’s not how I’ve done it, you are asking me to change the skills of my engineers, I don’t know if I have enough compute, I don’t have enough licenses from you”. All of these are solvable. But then when the complexity hit the walls, okay, it’s your choice.

“Do you want to have faster chips or not?”

SG: Exactly.

Chips to Systems

How did this tie into the shift to chiplets and these new chip designs, where you have lots of different tiles and you’re tying them together, and your overall company mantra of going from software to systems?

SG: The chiplets is driven by our customers envisioning an architecture of their product, of their semiconductor chip. They could move that entire chip to the next process…

But it’s a monolithic chip. The yields are tough and a lot of stuff doesn’t need to be that fast.

SG: Exactly. Expensive, inefficient to move the whole thing. Then you start thinking architecturally, which part of it do I want to squeeze the best performance, the best power I can get, and which other piece of it, “Nah, it’s okay, I can stay on a two or three generation behind and it’s not going to impact the actual end product”. So, it started creating the concept of a chiplet, that was around the 2018-ish timeframe.

It introduced a lot more variables.

SG: Exactly. Yes, so as it introduces more variables, from a design point of view, we started looking at it from a — we introduced a product at the time, instead of doing a Design Compiler at a block level, can you do a Design Compiler at the chiplet level? We had the product, actually 3DIC Compilers, so can you compile it the chip at an architectural level and say these are the type of chiplets you need. Then the challenge moved from electronics architecture and design, it started becoming physical challenges — thermal, structure. When you stack those chips on top of each other, the heat-

Interference and things like those, yeah.

SG: Exactly. EMIR, the electromigration, the voltage drop, because of the interference, it became a completely different—

You’re worrying about electrons leaking, it’s a tough problem.

SG: It’s amazing. So, the challenge moved from just designing electronically-functioning chip to becoming a physical effect that’s going to throw it off completely, that’s where talking about variables increasing, you are right now bringing physics variable into the chip-design process.

Just as a side note, how much is backside power going to help with a lot of those challenges, where you’re moving the power on the opposite side from the communications layers? Is that going to make a big difference in terms of the simplicity of this?

SG: It will, it’s an evolution when you move from planar to FinFET.

Yep, and now we’re going to Gate-All-Around.

SG: Then you Gate-All-Around. Then within the Gate-All-Around, how do I pass power through the backside?

It makes sense they come together because the transistors are getting more complicated on top.

SG: Right. That’s the beauty of free engineering innovation that you go through when you hit the wall, either of electronics or physics, etc. Then you start looking at this, you zoom out, you look at the system level and say, “Okay, if I partition it differently, if I architected it differently”, but the moment you start thinking this way, you need the sophisticated EDA to do it. That’s why when you asked in the beginning, “Why is Synopsys or our industries getting elevated?”, before we played an enablement role, right now we are actually empowering that next version of innovation in the semiconductor.

When you think about if people say, “Synopsys competitor”, they’ll say Cadence or whatever it might be, is probably the most obvious one, is there a bit where actually the potential competition — and a big shift for you has been designing or adding software for fabless chip companies to now software for hyperscalers, for example. They all have their own chips in AWS or Facebook, obviously, Apple. Is there a bit where actually that means your competition is more like a level of abstraction up? So you have someone like Arm who’s out there talking about, “Look, chips are super expensive to design, they’re harder than ever, just let us do the whole chip”, and that’s actually a level-up in terms of abstraction.

SG: Yeah, it’s a different solution. Say, Arm right now as they’re doing exactly what you described with the compute subsystem, instead of delivering the core, I can do the compute subsystem.

They’re going to chips to systems, too.

SG: Right. For us, it’s a fantastic opportunity with Arm and with the customer because as Arm is elevating that level of abstraction, they’re using more of our IP, more of our EDA, etc.

How much of a chip, if say a Facebook comes along, they would make a chip, or Microsoft, they just started a chip effort, or they’ve had one going on, but how much of their own IP or they actually bring, as opposed to pulling all these Lego blocks for all the different pieces?

SG: It’s Lego blocks, but they have their own differentiated piece of IT.

Is it like a small percentage? A large percentage?

SG: They’re focusing, their energy is, and I’m sure you’re very familiar with a workload-defined silicon or software-defined silicon, where they focus on are their own accelerators because they do not want a general purpose accelerator for the workload.

They want to fit their software.

SG: Because you may have 70% of the chip, it has no purpose for their application, they only want that 30% of the chip. So how do they design a chip specifically for their workload? They only know their workload. Let’s say if you’re a semiconductor company trying to design for them, you do not know their workload, even if they give it to you, it’s not a business for you. Meaning, if you’re a semiconductor company designing that chip just for that workload, you’re not going to make money. That’s why you see right now a huge beneficiary of this trend are ASIC providers because their job is to take a spec from the customer and design the rest of the implementation.

But the ASIC is just the customer doing themselves, that’s the real possibility, yeah.

SG: Exactly, it’s optionality. If they don’t have the resources to do it, they outsource it. So now how does Synopsys play a bigger role there? If you’re a hyperscaler or a system company, you’re trying to architect the system and the electronics in that system.

And your system is a lot broader than necessarily the system that you’re talking about.

SG: Exactly.

It is data center, power, cooling, networking.

SG: Exactly, and that’s why you have multiple level of systems. So you have the blade, the rack, then the whole data center, etc. So we started investing about seven-ish years ago or so in virtualizing chips.

Well, I’m glad we’re here because we’d never quite got to the virtualization bit and the Ansys acquisition so let’s wrap up there.

SG: This is where what we’re selling to a system company, let’s say hyperscaler, it’s in a way different than what we’ve been selling for semiconductor companies. Because a semiconductor company, if you go to them and say, “I can virtualize that chip”, like, “I don’t care”, but the system company is like, “No, of course, I care”.

Right. Before they design the chip, they need to design the data center, and they need a manifestation of that chip in that design to sort of sketch it all out before they actually start fabbing them.

SG: Exactly. Think of it the industry terms of the digital twin, so you’re creating a digital twin for chips. That has been an investment and a pivot we started pulling, but those are very specific to markets.

That’s a hyperscaler product.

SG: Yeah. What you do for hyperscaler is different than what you do for automotive because the type of chip, the type of virtualization, what they care about is very different.

So how does Ansys fit into this?

SG: So what Ansys brings in, actually Ansys brings in two areas of value that today, I want to say, the industry is desperate for solutions and innovation. One, at the advanced package, the IC Multi-Die that we talked about, given thermal structure, fluid dynamics, etc., are a challenge. You’re bringing those physics during the chip.

That’s what I was thinking about, as I was reading about this, is it really is a fluid dynamics question. That was the exact thing I was thinking about, which is still basically impossible to model, but we’re a little better than we were twenty years ago, but it’s definitely on the cutting edge.

SG: But the same thing, if you remember about the 16nm era, timing was okay. Power became a challenge, how to model and design for it. Right now, timing and power are very well-modeled, but how do I model thermal heat during the design phase?

Right, because you don’t want to find out once you’ve already started making the chip.

SG: That typically is what’s happening. Later, after you finished the electronic design and implemented-

Yep, there’s been some good examples of that recently.

SG: (laughing) Exactly. Then how do you do it early into that? So this is what I call it in the core chip design silicon. At the system level, my favorite example here would be a car. Today when you do a lot of the structural testing and design and simulation, a lot of it is physical, meaning it’s a real world test where you crash the car into a wall with a bunch of sensors and then you take measurements. It’s expensive, it’s slow, etc. Now the more electronics you’re going to have in a car that’s going to drive electronics are driving a physical function, that’s the purpose of it, how do you model that whole system from electronics and the rest of the physics to create a digital twin of a product? What Ansys brings in is simulation and analysis of multiple physics.

Yep, it’s the physics addition to this variable constraint bucket.

SG: Not to design it, to simulate it. So they have that simulation and analysis for various part of physics. Now, these physics are going to be triggered by electronics and with the way we envision Synopsys of the future with products being re-engineered to become more intelligent.

Right. So the system isn’t just a bunch of chiplets on a chip, that’s a system, it’s the entire package and it’s the product.

SG: Exactly. It’s all a layer of abstraction from the multiple chips in a package to all the way to the electronic system to the end product, the actual car.

One quick question, I know we’ve gone a little long. Jensen Huang’s been talking about actually generative AI in terms like transformer-based sort models in terms of chip design. Is that a viable approach? I mean, you’re doing AI, but it’s not necessarily that approach. Is that a real thing?

SG: Yes.

How does that change? Does that change the way you work again, or is it just a refinement of what you’re already doing?

SG: So the way we’re defining generative AI are in two buckets. The first one is can you have an AI assistant that helps you think of it like a co-pilot to bring a less experienced engineer faster in terms of their skills, or a skilled engineer to do less work.

Got it, so this is almost like a code assistant sort of idea.

SG: That’s one. So that’s actually, we do have products in early engagement with customers to get their feedback. The other part, can you truly have part of the chip to be done autonomously where you do not need, you can skip it from the way the workflow is and have it autonomously created and generated using a training and models? Yes, we believe that the answer is yes. The which part of that chip design, we have some ideas.

Well, the big thing is, though, I think the key applications where generative AI are really compelling is when you have a validation function, and that’s a huge part of what you do. So in some respects, because it has to be perfect, because you know if it works or doesn’t, that counter-intuitively makes this more possible in the long run.

SG: Yes, but actually you’re bringing up a good point. You know, when LLMs around, say, ChatGPT came about, “Hey, it’s not 100% accurate”, and it was like, “Ah, but this is okay, look how great it gave me nice jumpstart”, right? Of course, it will evolve over time, the more you train it, the more accurate it gets. In our world, you cannot be, “Hey, it’s just good enough”.

That’s right.

SG: Because then you go to manufacturing, you spend hundreds of million, the chip does not work, so you have gates that you go through in the design flow. How will gen AI change the design flow? The workflow is going to change, it will change. Which part of it has enough fidelity and gates of sign-off before you go to the next gate, to the next gate, so you’re not at gate number five and your realize gate number two was not accurate, then you have to look back? But it will change. I personally believe five-ish to seven years from now, many aspect of the chip design workflow will absolutely change with generative AI.

Sassine Ghazi, it was great to meet you. Great to learn about the world of Synopsys, I’d love to talk again sometime.

SG: Fantastic, it was my pleasure. Thank you.

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