An interview with Arm CEO Rene Haas about building subsystems on the leading edge and evolving Arm’s business model.
Instacart IPO, Instacart Conflict, Arm’s IPO Pop
Instacart is two different companies in one: the tech company is dependent on but in some respects in conflict with the logistics one. Then, ARM pops.
Arm’s F-1, Arm’s Risks, Arm’s Price
Arm’s F-1 is out, and while there is a reasonable plan for growth, its hard to justify the price Softbank is hoping for.
An Interview with Qualcomm CEO Cristiano Amon
An interview with Qualcomm CEO Cristiano Amon about his history at the company, why Qualcomm is more than a mobile company, and why semiconductors are the future.
An Interview With Jay Goldberg About the Chip Slowdown, Intel and Nvidia, and the CHIPS Act
An Interview With Jay Goldberg About the Chip Slowdown, Intel and Nvidia, and the CHIPS Act, plus Nvidia’s perfect storm, the importance of software versus chip design, and why Goldberg is so optimistic about ARM in the data center.
An Interview with “Father of the iPod” Tony Fadell
An interview with Tony Fadell about the iPod, iPhone, Apple’s history with Samsung, Nest, the future of ARM, and his new book “Build”.
An Interview with Nvidia CEO Jensen Huang about Manufacturing Intelligence
An Interview with Nvidia CEO Jensen Huang about the history of Nvidia, manufacturing intelligence, and how GPUs undergird Aggregation Theory.
Peloton’s Operations, Intel Buys Tower Semiconductor, What Now for ARM (plus Intel + RISC-V)
One more point on Peloton’s poor operations, then more news from the chip industry: Intel makes an acquisition and ARM is on its own.
Intel Earnings; An Interview with Jay Goldberg About Nvidia, ARM, and Intel
Intel’s earnings showed lower margins, and it won’t be the last time. Then, an interview with Jay Goldberg About Nvidia, ARM, and Intel.
Mr. CISC vs. Mr. RISC, ARM and AMD Threats, Gelsinger’s Three Tenets
The best way to understand Pat Gelsingers thinking about the threats posed by ARM and AMD is to go back to his arguments in favor of CISC over RISC